IR2213S |
RFQ for IR2213S Required Field |
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| Technical/Catalog Information | IR2213S |
| Vendor | International Rectifier |
| Category | Integrated Circuits (ICs) |
| Configuration | High and Low Side |
| Voltage - Supply | 12 V ~ 20 V |
| Current - Peak | 2A |
| Delay Time | 280ns |
| Package / Case | 16-SOIC (7.5mm Width) |
| Packaging | Tube |
| Number of Outputs | 2 |
| Input Type | Non-Inverting |
| Number of Configurations | 1 |
| Operating Temperature | -40°C ~ 125°C |
| High Side Voltage - Max (Bootstrap) | 1200V |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | IR2213S IR2213S |
| Product | Manufacturers | Pack | D/C |
| IR2213S | - | SOP | 06+ |
The IR2213(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 1200 volts.
Features |
| • Floating channel designed for bootstrap operation Fully operational to +1200V Tolerant to negative transient voltage dV/dt immune• Gate drive supply range from 12 to 20V• Undervoltage lockout for both channels• 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset• CMOS Schmitt-triggered inputs with pull-down• Cycle by cycle edge-triggered shutdown logic• Matched propagation delay for both channels• Outputs in phase with inputs• Also available LEAD-FREE (PbF) |
| Symbol | Definition | Min. | Max. | Units | |
| VB | High Side Floating Supply Voltage | -0.3 | 1225 | V | |
| VS | High Side Floating Supply Offset Voltage | VB - 25 | VB + 0.3 | ||
| VHO | High Side Floating Output Voltage | VS - 0.3 | VB + 0.3 | ||
| VCC | Low Side Fixed Supply Voltage | -0.3 | 25 | ||
| VLO | Low Side Output Voltage | -0.3 | VCC + 0.3 | ||
| VDD | Logic Supply Voltage | -0.3 | VSS + 25 | ||
| VSS | Logic Supply Offset Voltage | VCC - 25 | VCC + 0.3 | ||
| VIN | Logic Input Voltage (HIN, LIN & SD) | VSS - 0.3 | VDD + 0.3 | ||
| dVs/dt | Allowable Offset Supply Voltage Transient (Figure 2) | - | 50 | V/ns | |
| PD | Package Power Dissipation @ TA +25°C | (14 Lead DIP) | - | 1.6 | W |
| (16 Lead SOIC) | - | 1.25 | |||
| RJA | Thermal Resistance, Junction to Ambient | (14 Lead DIP) | - | 75 | /W |
| (16 Lead SOIC) | - | 100 | |||
| TJ | Junction Temperature | - | 125 | ||
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